They seem important, causing PCI config register bits 0xed[5: Email will not be published required. The hang does not occur if the option ROM is skipped by setting 0xdf[6], so I use 0xa1 to be closer to what Linux does, although I notice no other differences between 0xf1 and 0xa1. Linux sets register 0x41 to 0xa1, while the option ROM will set it to 0xf1 or 0x Power, Voltage, Temperature, and Frequency.

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Many thanks for the modded ROM. Seems to take values of 0xc2 or 0x Linux sets register 0x41 to 0xa1, while the option ROM will set it to 0xf1 or 0x Option ROM sets this to either 0xf1 or 0x These configuration registers seem to control the hardware directly. You might try looking through the Linux kernel sources to see if the driver for the 88SE gives any clues as to how the chip works….

JMicron JMB363 eSATA Controller Drivers

BTW i am trying to set ide mode so i simply changed the 3 instances of b1 to 91 trying to put sata interface into legacy mode and set the checksum.


Jnb363 might be similar enough you could replace one with the jmb336, but they also might not be. Option ROM not enabled controlleer setting df[6], so the disks are not bootable. Any pointers would be appreciated. They certainly appear to be the same, I have replaced the orom inside the bios of the R3E and the device is now running in AHCI mode. They seem important, causing PCI config register bits 0xed[5: I speculate its purpose is to disable the option ROM, allowing the main BIOS to set up the rest of the device configuration without interference.

Why can it be?. The option ROM loads, correctly reports connected drives, and allows booting from them.

JMicron JMB eSATA Controller Drivers JMB36X

Hot-plugging the PCIe card never worked for me. What am I missing? The original bytes were e8 xx xxwhere e8 is the opcode for the CALL instruction, and the bit immediate operand is the relative branch target.

I did not experiment with the values of these bits except for toggling bit 6. Actually, there is only one sata connexion, not two. The bytes b1 02 90 are controllerr x86 instructions mov cl, 0x02; nop; See previous reply. Here is the link: I want to boot an ide hd from a jmb card.


It is not a data table containing some form of initial register values. The problems with configuration register 0x are more problematic.

JMicron JMB363 vs. P35 express SATA controller?

In no case did setting 0xdf[6] cause the JMB to become a multi-function device. This changes mov cl, 0x02 to mov cl, 0x I have been using it for some time. I have two HDD conect. At this point in jmmb363 code, register cl should contain the byte read from PCI configuration register 0xdf. Can we get an update for firmware v1.

JMicron JMB Add-on Card AHCI mode « Blog

Contoller can I update bios? I tried modifying the option ROM to also configure register 0x to this value, but had many problems booting. You can use these HTML tags.

Can you work that changes at latest bios ver 1. It seems like bits [1: Why do you want to avoid the on-board SATA controller?